Low Power CMOS Vedic Multiplier Design

Spring 2017

Performed research on designing low power CMOS Multiplier circuits using the Urdhva Tiryagbhyam Algorithm found in Vedic Mathematics. I implemented the circuits using structural Verilog, synthesized using Synopsys Design Compiler, and tested their effectiveness in lowering power consumption by comparing power analysis results with standard shift-add multipliers in Vivado.

Low Power Urdhva Tiryagbhyam Vedic Multipler Report (PDF, 2.5 MB)