2016-2017
Worked on two independent projects simulating RISC microprocessors. The first project was a behavioral simulation of a 5 stage pipelined MIPS CPU architecture in VHDL (RTL level). The second project was different in that all modules were written in Verilog and utilized a common bus architecture with the datapath controlled by a variety of finite state machines. Following behavioral simulation, the CPU was also fully synthesized (gate level) with the Synopsys Design Compiler using a 90nm process.
RISC Microprocessor Verilog Design and Synthesis (PDF, 40.3 MB)
Pipelined MIPS CPU in VHDL (PDF, 1.6 MB)
Single Cycle MIPS CPU in VHDL (PDF, 258 KB)
Simple MIPS Datapath in VHDL (PDF, 1.8 MB)